发明名称 |
NONVOLATILE SEMICONDUCTOR MEMORY |
摘要 |
A first memory cell block (10a) connected with one input of a sense amplifier (SA0) through a main bit line (MBL0) includes a series circuit of four memory cells (Ma0 - Ma3) connected to word lines (TWL0 - TWL3), respectively; and dummy cells (DMa0) connected to dummy word lines (TDWL0). The drain of each of the memory cells (Ma0 - Ma3) is connected with a first selection gate (TS1) through a sub-bit line (SBL0), while the drain of the dummy cell (DMaO) is connected with the first selection gate (TS1). A second memory cell block (10b) connected with the other input of the sense amplifier (Sa0) through a main bit complementary line (MBL1) also includes a dummy cell (DMb0) connected with a dummy word line (TDWL0).
|
申请公布号 |
WO0065601(A1) |
申请公布日期 |
2000.11.02 |
申请号 |
WO2000JP02653 |
申请日期 |
2000.04.21 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
MARUYAMA, TAKAFUMI;KOJIMA, MAKOTO |
分类号 |
G11C16/04;G11C16/06;G11C16/28;(IPC1-7):G11C16/06 |
主分类号 |
G11C16/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|