发明名称 |
Modular interconnection architecture for expandable multiprocessor engine, implementing a virtual bus hierarchy comprising a plurality of levels, each level comprising the same basic element |
摘要 |
The architecture has a first level of interconnection (MI) with connection agents linking multiprocessor modules and managing transactions between them, and a second level of interconnection (SI) with external connection nodes (NCEj) connecting nodes and managing transactions between them. Each external connection node has two identical agents (NCS'j, NCSj), connected back-to-back.
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申请公布号 |
EP1049018(A1) |
申请公布日期 |
2000.11.02 |
申请号 |
EP20000401036 |
申请日期 |
2000.04.13 |
申请人 |
BULL S.A. |
发明人 |
AUTECHAUD, JEAN-FRANCOIS |
分类号 |
G06F12/08;G06F15/173;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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