METHOD AND DEVICE FOR SECTIONING MEMORY

摘要

PROBLEM TO BE SOLVED: To suppress a defect while maintaining a cache coherence domain by performing address inspection before data intercepted by a memory controller are processed. SOLUTION: When a request discriminated by a transaction(TR) type 241 is sent onto a system bus 100, the memory controller 200 snoop on the bus through a TR manager 201 and inputs a TR descriptor 210 to a slot of a pending buffer 202. When the descriptor 210 shows a write TR, the TR manager 201 sends a request to make a queue 230 acquire data 242 on the bus to a DRAM controller 220 to file the data. The controller 220 determines whether or not a section with a given address is ineffective, but when it is determined that access is illegal, the data from the queue 230 are discarded and the violating processor is reset.