| 摘要 |
<p>A first memory cell block (10a) connected with one input of a sense amplifier (SA0) through a main bit line (MBL0) includes a series circuit of four memory cells (Ma0 - Ma3) connected to word lines (TWL0 - TWL3), respectively; and dummy cells (DMa0) connected to dummy word lines (TDWL0). The drain of each of the memory cells (Ma0 - Ma3) is connected with a first selection gate (TS1) through a sub-bit line (SBL0), while the drain of the dummy cell (DMaO) is connected with the first selection gate (TS1). A second memory cell block (10b) connected with the other input of the sense amplifier (Sa0) through a main bit complementary line (MBL1) also includes a dummy cell (DMb0) connected with a dummy word line (TDWL0).</p> |
