SINGLE INSTRUCTION MULTIPLE DATA PROCESSING WITH COMBINED SCALAR/VECTOR OPERATIONS

摘要

PURPOSE: A method for processing signal instruction multiple data with a scalar/vector computation is provided to use a single instruction multiple data architecture having a RISC type instruction set, so that a programmer easily adapts to a programming environment of a vector processor based on a user friendly programming environment of a universal processor. CONSTITUTION: A multimedia processor(100) includes a processing core(105) which includes a universal processor(110) and a vector processor(120). The processing core(105) is connected with the remaining portion of the multimedia processor(100) through a cache sub-system(130) which includes a SRAM(160 and 190), a ROM(170) and a cache controller(180). The cache controller(180) configures a SRAM(160) based on an instruction cache(162) and a data cache(164) for the processor(110) and configures the SRAM(190) based on the instruction processor(192) and the data cache(194) for the vector processor(120). An on-chip ROM(170) includes a data and instruction for the processor(110) and is configured as a cache. The cache sub-system(130) is connected with the processors(110 and 120) and is oriented to two system buses(140 and 150) and operates as a cache and switching station for the processors(110 and 120) and is connected with the device buses(140 and 150).