| 摘要 |
PURPOSE: A semiconductor memory device for using a column transmitting gate to a bit-line clamp is provided to reduce a layout region of a memory core circuit by forming an NMOS transistor on a bit-line. CONSTITUTION: A pair of bit-lines(bit,/bit) is coupled to a memory cell(2). A pair of read-data-bus-lines(RDB,/RDB) receives output data from the pair of bit-lines. A pair of write data bus-lines(WDB,/WDB) transmits input data to the pair of bit-lines. A data input driver(4) drives an input data(DIN) to the pair of write data bus-lines, in response to a first write enable signal(WEI). The source and gate of a pair of first NMOS transistors(Q23,Q24) are connected to a power source(Vcc); and the drain thereof is connected to the pair of bit-lines to clamp. The drain-source path of PMOS transistors(Q27,Q28) is connected to between the pairs of the bit-lines and the read data bus-lines; and the gate thereof receives a first column signal(/yi). The source-drain path of PMOS transistor(Q29,Q30) is connected to between the pairs of the read data bus-lines and the write data bus-lines; and the gate thereof receives a second write enable signal(/WED). A pair of NMOS transistors(Q21,Q22) receives a second column control signal(wyi) at its gate; and clamps the pair of bit-lines. The source-drain path of NMOS transistor(Q25,Q26) is connected to between the power source(Vcc) and the pair of read data bus lines; and the gate thereof receives a write recovery signal(WR).
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