A CIRCUIT TO ELIMINATE AN OUTPUT CLOCK LOSS OF PHASE LOCKED LOOP REGENERATOR

摘要

PURPOSE: An output clock loss prevention device of a phase locked clock regenerator loop is provided to remove output clock error by dividing the frequency of the reference clock input to the clock regenerator much longer than the input reference clock. CONSTITUTION: A frequency divider divides the frequency of unstable reference clock input from a clock board. The frequency divider provides the reference clock to a PLL(phase locked loop) installed in an IC(integrated circuit) and a reference input pin of this IC. A processor controller adjusts or controls the frequency of the input reference clock and PLL output clock from the IC.