MEMORY DEVICE HAVING SEPERATED CLOCK INPUT BUFFER

摘要

PURPOSE: A semiconductor memory device with a separated clock input buffer is provided to make an access time with high speed and reduce a consumption of electric power at stand-by mode by separately disposing a first clock input buffer for generating an enable signal of a data input buffer and a second clock input buffer for generating a signal to latch an input signal. CONSTITUTION: A first clock input buffer(10) buffers and outputs an applied clock signal in order to output data on an output pad(DQ pad). An output-enable-signal generator(30) an output-enable-signal by using a signal (clkt2) which is generated by inverting an output signal of a first clock input buffer. A data output buffer(40) buffers an output signal and read signal of the output-enable-signal generator(30) to output the same. An input signal buffer(50) buffers and outputs an input signal in order to latch an external input signal. A delay circuit(60) delays an output signal of the input signal buffer(50), for a certain time. A latch signal(70) latches he output signal buffer(50) by using a signal(clkt4) outputted through a second clock input buffer(90) for buffering and outputting a clock signal applied thereto and a buffering unit(20) composed of an odd number of invertor.