COORDINATION AND SYNCHRONIZATION OF AN ASYMMETRIC SINGLE-CHIP DUAL MULTIPROCESSOR

摘要

PURPOSE: An interface and synchronization of an asymmetry single chip dual multi-processor are provided to improve the efficiency of a calculation function in a synchronizing process by using a vector coprocessor. CONSTITUTION: A multi-processor(100) is composed of a general processor(110) and a vector coprocessor(120). The general processor(110) and the vector coprocessor(120) are connected with another on-chip elements of the multi-processor(100) through a cache sub system(130) including SRAMs(160,190), a ROM(170), and a cache controller(180). The multi-processor(100) arranges the SRAM(160) to a shape of a command cache(162) and a data cache(164) for general processor(110). The multi-processor(100) arranges the SRAM(190) to a shape of a command cache(192) and a data cache(194) for vector coprocessor(120).