发明名称 |
HIGH-SPEED SYNCHRONOUS COUNTER CIRCUITRY |
摘要 |
Digital counter register stages RCRG(N) are constructed as twoto-one mux registers, each employing a multiplexer stage (113) having first, second, and third inputs (S0, I0, I1) and an output (116) connected to the switching signal input (D) of a D-type flip-flop (15), whose Q output comprises a first input (I1) to the multiplexer stage (113). An inverter buffer (19) is associated with each register stage (RCRG(N)) and has an input connected to the output (Q) of said D-type flip-flop (115) and an output connected to the second input (I0) of the multiplexer stage (RCRG(N)) and fed forward to a NOR gate (21) associated with each subsequent register stage (RCRG(N)).
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申请公布号 |
CA2175614(C) |
申请公布日期 |
2000.10.31 |
申请号 |
CA19962175614 |
申请日期 |
1996.05.02 |
申请人 |
HE HOLDINGS, INC. D/B/A HUGHES ELECTRONICS |
发明人 |
CHINN, GREGSON D.;ODA, DWIGHT N. |
分类号 |
H03K23/00;H03K23/40;H03K23/50;(IPC1-7):G06M1/00 |
主分类号 |
H03K23/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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