发明名称 |
Data processor which accesses a second memory while responding to an interrupt request during programming and erasing mode of first erasable and programmable non-volatile memory |
摘要 |
To obtain a correct vector address even if an interrupt occurs during erasing or programing of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.
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申请公布号 |
US6141700(A) |
申请公布日期 |
2000.10.31 |
申请号 |
US19990263917 |
申请日期 |
1999.03.05 |
申请人 |
HITACHI, LTD. |
发明人 |
IWATA, KATSUMI |
分类号 |
G11C17/00;G06F9/22;G06F9/24;G06F9/445;G06F9/46;G06F9/48;G06F11/00;G06F11/14;G06F12/06;G06F13/00;G06F15/78;G11C16/02;(IPC1-7):G06F13/00 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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