Post etch silicide formation using dielectric etchback after global planarization

摘要

The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming a masking layer over a semiconductor substrate such that the gate conductor is substantially covered by the masking layer. The masking layer is preferably planarized using any of a variety of well known techniques. After planarization of the masking layer, the masking layer is etched such that an upper surface of the gate conductor is exposed. A silicide layer is preferably formed upon the upper surface of the gate conductor. The masking layer prevents the concurrent formation of silicide upon the source/drain regions.