| 摘要 |
A pickup reads data recorded on a disk and outputs a current signal corresponding to the read data. An amplifier outputs the current signal as a voltage signal. A data slice circuit binarizes the voltage signal and converts it into an EFM signal. In response to the EFM signal, a PLL circuit generates a PLL clock signal in synchronization with a reproduction speed. When a reference speed or its two-times higher speed is selected as the reproduction speed, if the PLL clock signal is synchronized with the EFM signal, the frequency of the PLL clock signal is proportionate to the reproduction speed. In response to the PLL clock signal, the data slice circuit controls the frequency band of a reference voltage in accordance with the reproduction speed, and outputs the EFM signal. A data processing circuit demodulates the EFM signal and removes a jitter from the demodulated signal in response to the PLL clock signal. The data processing circuit also corrects an error of data corresponding to the demodulated signal in response to the PLL clock signal, and outputs audio data.
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