发明名称 |
Dual damascene processing for semiconductor chip interconnects |
摘要 |
The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.
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申请公布号 |
US6140226(A) |
申请公布日期 |
2000.10.31 |
申请号 |
US19980126212 |
申请日期 |
1998.07.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GRILL, ALFRED;HUMMEL, JOHN PATRICK;JAHNES, CHRISTOPHER VINCENT;PATEL, VISHNUBHAI VITTHALBHAI;SAENGER, KATHERINE LYNN |
分类号 |
H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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