Method and apparatus for conducting failure analysis on IC chip package

摘要

The present invention is concerned with a method and apparatus for performing a failure analysis on an integrated circuit chip package by mounting the package in a printed circuit board that is equipped with a recess (or an aperture) adapted for receiving the package and then making an electrical connection between the pin leads on the package and the terminals on the board such that when a backside surface layer of the package is later removed to expose the active circuit in the chip, the electrical connection between the chip and the board is substantially maintained so that a bias voltage can be fed into the chip to perform the failure analysis.