发明名称 |
Hierarchical clock line tree design method for application specific integrated circuit, involves connecting clock line trees of same structure with clock signal input terminals of hierarchical structures |
摘要 |
An integrated circuit (1) has hierarchical structures (11-13) with clock signal input terminals (14-16,17-20,21). The clock line trees of same structure are connected with the input terminals.
|
申请公布号 |
DE10008585(A1) |
申请公布日期 |
2000.10.26 |
申请号 |
DE20001008585 |
申请日期 |
2000.02.24 |
申请人 |
NEC CORP., TOKIO/TOKYO |
发明人 |
HIROSE, KENJI |
分类号 |
H01L21/82;G06F1/10;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
H01L21/82 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|