Pulse generating circuit includes delay circuit and invertor where outputs are input to AND circuit

摘要

The output of N-MOS transistor (2) is input to invertor (6) and output of delay circuit (7) and output of invertor (6) are input to AND circuit (8). Output of AND circuit is input to gate of N-MOS transistor (9) having drain connected to output line (10), when clock signal input to N-MOS transistor (2) changes from low to high level. Voltage of output line performs transition from high to low level.