PACKET COMMAND DRIVING TYPE MEMORY

摘要

PURPOSE: A packet command driving type memory is provided which prevents the generation of glitch through assuring margin and also prevents the generation of wrong address. CONSTITUTION: An address generating circuit inputs an external address and generates a corresponding internal address from the external address. The address generation circuit of a packet command driving type memory comprises: a level conversion part(3-1) inputting a packet address by synchronizing it to a clock and converting an input level of the packet address to an internal circuit operation level; a first flip flop(3-2) inputting the output of the level conversion part by synchronizing to a first edge of the clock; a second flip flop(3-3) outputting a first enable signal generated during inputting an external address by synchronizing to a second edge of the clock; a third flip flop(3-4) inputting a second enable signal by synchronizing to the first edge of the clock; a latch part(3-5) inputting the output of the first flip flop and the second flip flop; an enable time delaying unit(12) delivering the clock to the falling edge of the second flip flop in order for the latch part to operate; a logic part(3-6) assembling the output of the third flip flop and a selection signal; and an output part(3-7) outputting the output of the latch part in response to the output of the logic part.