PRECHARGE CONTROL CIRCUIT FOR DETECTING WRITING DEFECT OF SYNCHRONOUS DRAM

摘要

PURPOSE: A precharge control circuit for detecting writing defect of a synchronous DRAM is provided to improve the package yield by reducing the test time by minimizing the precharge path during the write defect detection test of the synchronous DRAM. CONSTITUTION: A precharge control circuit detects writing defect of a synchronous DRAM. The precharge control circuit comprises: a block selection information input unit which delays block selection information applied from a row decoder, and outputs the delayed signal; a row address input unit outputting by assembling a row address decoded in the row decoder with the delayed block selection information; a precharge control unit(47) transferring a precharge control signal in response to a mode register set information applied from the external during the test to detect the write defect; and a boost potential output unit assembling the precharge control signal and the output of the row address input unit and outputting it as a boost potential. The precharge control circuit reduces the overall test time by minimizing the precharge path using MRS(Mode Register Set) information during tRDL item test of the wafer test, and also improves the yield in the package level.