发明名称 MEMORY CONTROLLING APPARATUS OF DIGITAL TV
摘要 PURPOSE: A memory controlling apparatus of a digital TV is provided to read and write an analog image in a block unit from/to the memory, thereby commonly using one address decoder with respect to all input images. CONSTITUTION: The memory controlling apparatus of a digital TV comprises an input mode decoder(301) for discriminating a sampling frequency ratio of a luminance and a color difference signal from an input image and thus outputting a selecting signal, a luminance/color signal and a reading/writing signal, an address decoder(302) for reading data output from the input mode decoder and then generating a physical address for reading and writing the data, a memory controlling and interceding portion(303) for reading the data stored in an address generated by the address decoder or writing a data to the address, and an external memory(304) for performing the reading/writing function by the control of the memory controlling and interceding portion. In the input mode decoder, the sampling frequency ratio of the luminance and the color difference signal is selected out of 4:4:4, 4:2:2 and 4:2:0.
申请公布号 KR20000061569(A) 申请公布日期 2000.10.25
申请号 KR19990010686 申请日期 1999.03.27
申请人 LG ELECTRONICS INC. 发明人 KIM, SEONG YONG
分类号 H04N7/24;(IPC1-7):H04N7/24 主分类号 H04N7/24
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