| 摘要 |
Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns. The second insulating layer includes therein first contact holes that selectively expose the first conductive layer patterns. A first level interconnection is formed in the first contact holes and on the second insulating layer to electrically contact the first conductive patterns and to selectively electrically interconnect selected ones of the first conductive patterns to one another on the second insulating layer. A third insulating layer is formed on the second insulating layer and on the first level interconnection. The third insulating layer includes therein second contact holes that selectively expose the first level interconnection and selected ones of the capacitors. A second level interconnection is formed in the second contact holes and on the third insulating layer to selectively electrically interconnect the at least one of the first capacitors, to selectively electrically contact the first level interconnection and to selectively electrically interconnect selective ones of the at least a second of the capacitors to one another and to the first level interconnection. |
