发明名称 |
Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer |
摘要 |
The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 ANGSTROM to about 800 ANGSTROM having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.
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申请公布号 |
US6137126(A) |
申请公布日期 |
2000.10.24 |
申请号 |
US19990375499 |
申请日期 |
1999.08.17 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
AVANZINO, STEVEN C.;NGO, MINH VAN;HUI, ANGELA T.;JIANG, CHUN;PARTOVI, HAMID |
分类号 |
H01L21/336;H01L21/768;H01L29/49;(IPC1-7):H01L29/72;H01L27/10 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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