Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure

摘要

A memory device has a plurality of memory cells formed in rows and columns. Each memory cell includes an erasable Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. The memory device utilizes a plurality of erase lines which are connected to p- wells which, in turn, are capacitively coupled to the floating gates of the memory transistors to provide electrical erasability.