| 摘要 |
An input receiver circuit which is capable of reducing a difference between a propagation time at the rise-up and that at the fall of an input signal and is suitably used for semiconductor memory devices. The input receiving circuit comprises a node, six N channel (N-ch) MOS transistors and two P channel (P-ch) MOS transistors. The first and second N-ch transistors receive an activation signal and have grounded sources. The third and fourth N-ch transistors receive the first and second signal and have sources connected to the drains of the first and second N-ch transistors, respectively. The fifth and sixth N-ch transistors have gates connected to the node and are provided in parallel to the third and fourth N-ch transistors, respectively. Sources of the first and second P-ch transistors are supplied with the power source voltage. Drains of the first and second P-ch transistors are connected to the drains of the third and fourth N-ch transistors, respectively. Gates of the first and second P-ch transistors are connected to the node. The second P-ch transistor outputs a drain voltage as an output signal.
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