| 摘要 |
A method for manufacturing a self-aligned stacked storage node DRAM cell on a substrate for a capacitor over bit line (COB) process is disclosed. The method comprises the steps of: forming a first planarized dielectric layer onto the substrate; forming a first planarized barrier layer onto the first dielectric layer; patterning and etching the first barrier layer until the first dielectric layer is reached to form a bit line contact and a storage node contact; forming first sidewall barrier spacers on the sides of the first barrier layer; etching the first dielectric layer until the substrate is reached to form a bit line contact opening and a storage node contact opening; depositing a first conducting layer into and above the bit line contact opening and the storage node contact opening and above the first barrier layer and the first sidewall spacers; depositing a second conducting layer onto the first conducting layer; depositing a cap barrier layer atop the second conducting layer; patterning and etching the first conducting layer, the second conducting layer, and the cap barrier layer to form an intermediate structure above the bit line contact opening and a plug in the storage node opening; forming second sidewall barrier spacers on the sides of the intermediate structure; forming a second dielectric layer onto exposed portions of the first and the second sidewall barrier spacers, the plug and the cap barrier layer; patterning and etching the second dielectric layer leaving a remaining portion only on the intermediate structure; forming a third conducting layer onto exposed portions of the plug, the first and the second side wall barrier spacers, the cap barrier layer, and the remaining portion of the third dielectric layer; and removing the third conducting layer atop the second dielectric layer.
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