CMOS semiconductor device comprising graded N-LDD junctions with increased HCI lifetime

摘要

A CMOS semiconductor device is formed having an N-channel transistor comprising a source/drain region and an N-LDD region with a graded junction. The graded N-LDD junction is obtained by implanting a high diffusivity N-type impurity, such as P, after the N-LDD implant, e.g., As, subsequent to sidewall spacer formation. Upon activation annealing to form the N-channel transistor source/drain regions, P diffuses to a greater depth than As, thereby forming a deeper and graded N-LDD junction.