| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a computer which can shorten an evaluation period and a test period without the rewriting and the freezing of a register value by installing a bit which can collectively output writing permission signals to all control registers. SOLUTION: A first special bit 8 which collectively outputs writing permission signals to all control registers 11 and 14 is installed. In the computer, a central processing unit 1 outputs an address allocated to a first special address decoder 7 to an address bus 3 and outputs data which is to be written into the first special bit 8 to a data bus 4 in a state where an operation inhibition signal is outputted and the operation of an incorporated peripheral circuit is inhibited. The first special address decoder 7 outputs a first special access signal in synchronizing with a data enable signal and reading/writing signal. The first special bit 8 latches data at that time, holds the value and correspondingly outputs a collective writing signal.</p> |
