Semiconductor memory including an intermediate potential circuit capable of providing reduced current flow

摘要

A semiconductor memory enables establishment of intermediate electric potential of bus line to be implemented without flowing through current between a power-supply and ground. When a read-bus line 'RB' is of 'Low' state, high-pulse is outputted as an internal pulse signal 'RBEQ', then 'N'-type transistor N2 and 'P'-type transistor P2 become 'ON' state. Further, also 'N'-type transistor N5 becomes 'ON' state. Then, 'N'-type transistor N3 becomes 'OFF' state, 'N'-type transistor N4 becomes 'ON' state, also 'P'-type transistors P3, and P4 become 'ON' state. According to this situation, output of an inverter I2 becomes 'Low', 'P'-type transistor P1 becomes 'ON' state, 'N'-type transistor N1 becomes 'OFF' state, thus electric potential of the read-bus line 'RB' changes into 'High' from 'Low'. Subsequently, it makes signal 'RBEQ' 'Low', then, 'P'-type transistor P2 and 'N'-type transistor N2 become 'OFF' state so that the read-bus line 'RB' maintains intermediate potential level.