发明名称 |
PROCESSOR ELEMENT CIRCUIT, PARALLEL CALCULATION SYSTEM AND BUS BRIDGING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To reduce design man-hours of a processor element and a bus ridge circuit when a dedicated system is constructed as a parallel computer system by selecting an operation processing mode and a bridge mode and sharing the same LSI by a processor element and the bus bridge circuit. SOLUTION: This system is constituted of a host computer 11 and plural sheets of boards 12 on which many processor elements 14 are mounted. The host computer 11 and the respective boards 12 are connected to each other with a system bus 13. In the system, a mode selection means can select an operation processing mode and a bridge mode. A processor element circuit is used as the processor element 14 of a parallel calculation system by making it to be the operation processing mode or it can be used as a bus bridge circuit 17 for protocol conversion with the different bus of the parallel calculation system or as a part of it by making it to be the bridge mode. |
申请公布号 |
JP2000298654(A) |
申请公布日期 |
2000.10.24 |
申请号 |
JP19990106099 |
申请日期 |
1999.04.14 |
申请人 |
FUJI XEROX CO LTD;TAISHO PHARMACEUT CO LTD |
发明人 |
INAHATA SHINJIROU;YAMADA SOU;MIYAGAWA NOBUAKI;MURAKAMI KAZUAKI;TAKASHIMA HAJIME;KITAMURA KAZUYASU |
分类号 |
G06F15/173;G06F13/36;G06F17/10 |
主分类号 |
G06F15/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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