Digital bit synchronizer for low transition densities

摘要

An apparatus and method for synchronizing a derived bit clock with a transmit bit clock of a transmitted data signal is disclosed. The present invention uses a divide-only direct digital synthesizer and a fixed local oscillator. The synthesizer generates a derived bit clock by dividing the fixed, high frequency local oscillator. A transition detector identifies valid bit transitions in the unsynchronized data signal. At each valid transition, a control algorithm determines whether to adjust the frequency and/or phase of the derived data clock in order to maintain synchronization between the derived bit clock and the transmit bit clock. The unsynchronized data signal and the derived bit clock are processed by a reclock latch to generate a synchronized data signal.