Semiconductor memory device configured with I/O separation

摘要

A common line shared by the sources of the transistors configuring a read gate is arranged in a sense amplifier region. A voltage control circuit is arranged at an intersection of the sense amplifier region and a subordinate decoder region. The voltage control circuit supplies to the common line a ground voltage in reading data and a voltage higher than the ground voltage in writing data. As such, erroneous read operation or current leakage does not occur when a read column select gate turns on in writing data.