| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a layout method for reducing clock skew by which an appropriate design can be made by grasping accurate propagating delaying time and arranging position by easily performing simulation accompanying the layout of circuit elements. SOLUTION: In a layout method for reducing clock skew, clock skews are reduced by making the propagation delaying time uniform in such a way that a plurality of local buffers 3 is arranged around a global buffer 2 supplied with clock signals and the local buffers 3 are connected to the global buffer 2 through wires 4 having the same length. Then the flip flops 9 of many registers are arranged on bars (wires) 8 crossing the wires 7 extended by the same distance in a plurality of directions from the local buffers 3.</p> |
