| 摘要 |
PROBLEM TO BE SOLVED: To obtain a multiple-bit sift circuit which reduces delay time from the viewpoint of circuit delay and wire delay. SOLUTION: In a sequential shift processing by means of a shift quantity signal of this shift circuit, the circuit configuration is formed so that input data is selected without decoding a multiplexer M11 on a 1st stage or multiplexers M11 and M12 on the 1st and 2nd stages with the shift quantity signal, the multiplexer on the next stage is decoded in the meanwhile, and the delay time of the shift circuit is shortened. The circuit configurations of the next and succeeding stages are formed so that the input data selection numbers of a multiplexer are distributed and uniformized to reduce a wire load and an input load.
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