| 摘要 |
PROBLEM TO BE SOLVED: To compensate the phase jump being the cause of spuriousness, to simplify structure and to facilitate adjustment by delaying an output signal with a rounding error value at the time of converting the phase amplitude of data of a phase operation result. SOLUTION: DDS1 has a phase accumulator 12 which repetitively adds frequency data S generated by a frequency data setting circuit 11 in synchronizing with a reference clock fclock generated by a reference clock oscillator 2 and generates the phase signal P of m+n bits. A phase amplitude converter 13 inputs the high-order m bits M of the phase signal P and converts a sine wave amplitude signal A into an analog signal W' by a D/A converter 14. The low- order n bits N of the phase signal P and frequency data S are converted into a delay compensation signal D by a delay data converter 16 and it is converted into a delay compensation signal D' by a D/A converter 17. A variable delay unit 15 delays the analog signal W' in accordance with the delay compensation signal D', changes the phase of the analog signal W', compensates a rounding error at the time of changing the phase of the analog signal W' and outputs an output signal W.
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