发明名称 OSCILLATION STABLE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an oscillation stable circuit with higher efficiency. SOLUTION: The positive amplitude of the output signal 102 of a transmission circuit 1 is detected by a buffer 2 and negative amplitude is detected by an inverter 3. The number of output signals which the buffer 2 detects are counted by a counter 4 and a counter 5 counts the number of output signals that the inverter 3 detects. A judgement circuit 7 compares the identity of a positive amplitude counting number that the counter 4 counts and a negative amplitude counting number that the counter 5 counts. The outputs of clocks 110 and 111 outputted to the inner circuit of a clock generation circuit 8 are controlled according to a permission signal of the comparison result. Thus, oscillation stable time is secured, the number of the stages of the counter is reduced and time required for securing oscillation stable time can be shortened. When illegal oscillation exists, the value of the counter is shifted and therefore illegal oscillation can highly precisely be detected.
申请公布号 JP2000293258(A) 申请公布日期 2000.10.20
申请号 JP19990100671 申请日期 1999.04.07
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 MORI TOSHIYUKI
分类号 G06F1/04;H03K3/03;H03K21/08;(IPC1-7):G06F1/04 主分类号 G06F1/04
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