| 摘要 |
PROBLEM TO BE SOLVED: To reduce needed time when a CPU reads data from a storage device. SOLUTION: A ROM control circuit 36 is provided between a ROM 34 where a program for a CPU 3] is stored and a ROM bus 52, and data is read from the ROM 34 through the circuit 36. Also, when the CPU 31 reads the data of a certain address from the ROM 34, the circuit 36 reads the data of the next address preliminarily and holds it Since a program has high continuity, the data of the next address is frequently read in the next access by the CPU 31, and when the CPU 31 accesses the data of the preliminarily read address, the circuit 36 transmits the held data to the CPU 31.
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