发明名称 WARNING MASK CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the scale of hardware of the warning mask circuit by decreasing the number of demultiplexer/multiplexer circuits for a warning multiplex signal and the number of secondary warning mask circuits having been provided in the unit of multiplicity. SOLUTION: A recovery protection time 3 is read from a storage means 5 between the same address signals 1 by the address signal 1 synchronously with a phase of a warning multiplex signal, and written in the storage means 5 as a warning consecutive time 4. The warning consecutive time 4 is equal to a counter initial value S9 when a corresponding bit of the warning multiplex signal indicates 'with warning', and equal to an incremented value of the recovery protection time 3 when the bit indicates 'without warning'. However, when the value of the recovery protection time 3 reaches a preset value in a state of 'without warning', the recovery protection of host warning is released and the value of the recovery protection time 3 is maintained after that. Moreover, while the corresponding bit of the warning multiplex signal indicates 'with warning', the value of the recovery protection time 3 has the initial value and is at a halt.
申请公布号 JP2000295218(A) 申请公布日期 2000.10.20
申请号 JP19990096508 申请日期 1999.04.02
申请人 NEC ENG LTD 发明人 HAMADA SATOSHI
分类号 H04L29/14;H04L12/24;H04L12/26;(IPC1-7):H04L12/24 主分类号 H04L29/14
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