| 摘要 |
PROBLEM TO BE SOLVED: To realize a PLL whose C/N is excellent by preventing the generation of a through current not by outputting control signal pulses to a charge pump at the same time and generating a phase difference signal to eliminate a dead zone even when phase difference between a reference signal and a comparison signal is small. SOLUTION: A reference signal fr is inputted to the clock terminal CK of a D flip-flop 50. A comparison signal fp is inputted to the clock terminal CK of a D flip-flop 51. The data output terminals Q of the flip-flops 50 and 51 are connected to the input terminal of a two-input AND 52. Outputs of the AND 52 are connected to the reset terminals R of the flip-flops 50 and 51. The output terminal Q of the flip-flop 50 is connected to the input terminal of an inverter 53, and a phase difference signal (up) is outputted from the output terminal of the inverter 53. A phase difference signal down is outputted from the output terminal Q of the flip-flop 51 via a delay circuit 54. |
