| 摘要 |
PROBLEM TO BE SOLVED: To obtain a data evaluation circuit capable of evaluating bit deviation widely. SOLUTION: This data evaluation circuit outputs a signal S1 (n) obtained by shifting data Dm to be measured by n bits to comparator circuits 3 to 5. A memory 8 outputs expected value data designated by an address counter 7 to a shift register 2. The register 2 outputs the parallel output formed by a 1st bit S2 (1) to a 2n-th bit Sn (2n), to the circuits 3 to 5. When data is normal, the signal S1 (n) is equal to the signal S2 (n), and the circuit 4 becomes active. When (m) pieces of the data Dm are omitted, or when (m) pieces of illegal data are mixed, a comparator circuit corresponding to a signal S2 (n-m) or S2 (n+m) becomes active. The counter 7 is controlled based on a bit shift output signal Sb from a decision circuit 9. In the case of Sb=+m, the count value of the counter 7 is advanced by (m). In the case of Sb=-m, it is stopped for (m) counts of clocks Cd.
|
