| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM which can read out data at high speed. SOLUTION: This device is provided with a memory cell array 1, a row decoder 3 driving selectively a word line, a bit line sense amplifier 2 driven by a word line and detecting/amplifying data read out to plural bit lines by being controlled by a first sense amplifier activation signal, a column selection gate 5 driven by a column selection signal generated by being late in the first sense amplifier activation signal and connecting a selected bit line to a correspondent data line, and a data line sense amplifier connected to a data line, controlled by a second sense amplifier activation signal generated by being late in a column selection signal, and detecting/amplifying data transferred to a data line by the column selection gate 5 with the bit line sense amplifier 2.
|
