| 摘要 |
A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a master-slave flip-flop. An input clock signal having a frequency FN is supplied to the flip-flop of each circuit block, and an output clock signal having a frequency FN/2 or FN/3 is generated in response. A control signal supplied to the OR gate of the second circuit block determines whether the frequency will be divided by 2 or by 3. The circuit blocks generate differential output signals, and common-mode signals are generated for supply to the OR gate inputs by summing and dividing the differential output signals with high value resistors.
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