| 摘要 |
PROBLEM TO BE SOLVED: To provide high-accuracy latch-up verification to the layout data of a semiconductor integrated circuit. SOLUTION: In a method for verifying latch-up, such processes that well areas, transistor areas, and substrate contact areas are extracted from the layout data of a semiconductor integrated circuit and oversize values are individually set from the extracted information are sequentially executed. Then, after oversizes are sequentially executed (oversize areas demarcation) by using the set oversize values, verified results are outputted by regarding the transistor area existing outside an oversized substrate contact area as an error area.
|
