Clock period detection circuit for multiplier circuit, detects whether clock signal passes through detector or bypasses detector to output control signal, based on which clock period is detected

摘要

Clock signals (1) are input to parallely arranged delay detectors (2) whose delay time is varied step by step. The clock signal is passed through detector, latch and encoder or clock signal is directly passed through latch, to output the control signal. Based on the control signal, period of clock signal is detected.