Clock recovery apparatus

摘要

A reproduction signal (10) is processed in an AD converter (4) and an equalizer (16) to be a decoder input signal (12). The decoder input signal (12) is used to calculate a phase error signal (25) and a quality judgement signal (26). A phase-frequency error detection circuit (22) retains a sign of the phase error signal (25) obtained when the quality judgement signal (26) is changed in quality from "good" to "bad". The phase-frequency error detection circuit (22) then outputs, as a phase-frequency error signal (27), the phase error signal (25) when the signal quality is "good", and a given value corresponding to the retained sign when the signal quality is "bad". A voltage controlled oscillator (9) generates a recovered clock signal (11) whose frequency is based on the oscillation control signal (15) generated by the phase-frequency error signal (27). <IMAGE>