| 摘要 |
<p>A signal amplifying circuit (24) includes level shifting input circuits (D1-D4) permitting input common-mode voltages (VIN1 and VIN2) of an amplifier and fault detection circuit (50) to vary between preset limits. The sense amplifier circuit (24) includes a DC offset buffer circuit (52) operable to receive an analog DC offset compensation signal and provide this signal to an input of the amplifier and fault detection circuit (50). The buffered DC offset compensation signal provided to the amplifier and fault detection circuit (50) is operable to reduce an aggregate DC offset voltage attributable to signal amplifying circuit (24) to a desired DC offset level. The amplifier and fault detection circuit (50) also includes a fault detection function whereby an output (VSENSE) of the amplifier circuit (50) is forced to a predetermined output state if either, or both, of the inputs (VIN1 and VIN2) of the sense amplifier circuit (24) are unconnected; i.e., floating. The output (VSENSE) of the amplifier and fault detection circuit (50) is provided to an output buffer circuit (54) operable to modulate the load current supplied to an output (VOUT1, VOUT2) thereof as a function of a difference between the amplifier output signal (VSENSE) and the output buffer output signal (VOUT1). <IMAGE></p> |
