发明名称 |
Apparatus and method for generating a decoding clock signal in response to a period of write and read clock signals |
摘要 |
Disclosed is an apparatus and a method for generating decoding clock signals in response to a period of write and read clock signals for decoding transmission data, which is suppressed in a form of punctured code at a code rate. The apparatus according to the present invention comprises a) a clock generator receiving a control signal and a code rate from a transmission part, for rearranging a suppressed data; b) a controller receiving a write clock signal from an external circuit and a read clock signal from the clock generator, for controlling a period of a read clock signal wherein the period of the read clock signal is correspondent to the number of data stored in the memory; c) a decoding clock generator receiving a system clock signal from an external circuit and the control clock signal from the controller, for outputting a decoding clock signal.
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申请公布号 |
US6134288(A) |
申请公布日期 |
2000.10.17 |
申请号 |
US19970953009 |
申请日期 |
1997.10.16 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
BAEK, JONG SEOB |
分类号 |
H03M7/30;H04L1/00;H04L7/02;H04L13/08;H04L29/08;(IPC1-7):H04L7/00;H04L25/00;H04L25/40 |
主分类号 |
H03M7/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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