发明名称 Low temperature process for fabricating layered superlattice materials and making electronic devices including same
摘要 A liquid precursor containing thallium is applied to a first electrode, RTP baked at a temperature lower than 725 DEG C., and annealed at the same temperature for a time period from one to five hours to yield a ferroelectric layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature lower than 725 DEG C. If the material is strontium bismuth thallium tantalate, the precursor contains (m-1) mole-equivalents of strontium for each of (2.2-x) mole-equivalents of bismuth, x mole-equivalents of thallium, and m mole-equivalents of tantalum, where m=2 and 0.0<x</=2.2.
申请公布号 US6133092(A) 申请公布日期 2000.10.17
申请号 US19980122562 申请日期 1998.07.24
申请人 SYMETRIX CORPORATION;MATSUSHITA ELECTRONICS CORPORATION 发明人 HAYASHI, SHINICHIRO;PAZ DE ARAUJO, CARLOS A.
分类号 C23C18/12;H01L21/314;H01L21/316;H01L21/8246;H01L27/105;(IPC1-7):H01L21/824;H01L21/20 主分类号 C23C18/12
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