Redundancy decoding circuit having automatic deselection

摘要

A redundancy decoding circuit reduces standby power consumption in a memory device by automatically deactivating a deselect signal after a burst read/write operation, thereby eliminating a current path through the redundancy decoding circuit. The redundancy decoding circuit includes a pulse generator which generates a pulse signal having a predetermined pulse width that is just long enough to accommodate a read/write operation. The pulse signal is applied as the deselect signal to a drive circuit which provides drive current to a comparator for decoding a redundant address. A pulse begins when the chip select signal is activated and ends after a predetermined time. The pulse generator is implemented as plurality of series-connected flip-flops and a logic circuit for combining the outputs from the flip-flops which are clocked by a common clock signal.