| 摘要 |
A traceback processor of a survivor memory unit for use in a trellis-coded modulation decoder, wherein the survivor memory unit includes a data delay processor for providing determination vectors in parallel and the traceback processor for selectively providing one of an N1 and an N2 state mode decoded symbols, with decoding depths respectively corresponding to the N1 and N2 state mode decoded symbols being D1 and D2, is provided. A first traceback module iteratively calculates an N1 and an N2 state mode ith previous states and provides one of an N1 and an N2 state mode (D1-1)st previous states, i being an integer ranging from 1 to (D1-1). A second traceback module provides an N1 state mode decoded symbol and an N2 state mode (D1)th previous state and a third traceback module iteratively calculates an N2 state mode jth previous state, j being an integer ranging from (D1+1) to (D2-1). A fourth traceback module provides an N2 state mode decoded symbol and a first mode selector selectively provides one of the N1 and the N2 state mode decoded symbols.
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