发明名称 |
Semiconductor memory device with spare memory cell |
摘要 |
In an SDRAM, when a spare column selection line is not used, access to a column selection line is started at a first time at which complementary column address signals are defined, and access to the column selection line is stopped until a second time at which the level of a redundant column decoder activation signal is defined when the spare column selection line is used. Compared with the case in which access to the column selection line is always stopped until the second time, the access speed is increased.
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申请公布号 |
US6134681(A) |
申请公布日期 |
2000.10.17 |
申请号 |
US19980004299 |
申请日期 |
1998.01.08 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
AKAMATSU, HIROSHI;MORI, SHIGERU |
分类号 |
G11C11/407;G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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